Digital communication receivers must sample an incoming waveform and then reliably detect the sampled data. Typically, a receiver includes a CDR system to recover the clock and data from an incoming data stream. The CDR system generates a clock signal having the same frequency and phase as the incoming signal, which is then used to sample the received signal and detect the transmitted data.
U.S. patent application Ser. No. 10/965,138, filed Oct. 14, 2004, entitled “Parallel Sampled Multi Stage Decimated Digital Loop Filter for Clock/Data Recovery,” incorporated by reference herein, discloses a CDR architecture that uses an oversampled phase detector followed by a parallel sampled multi-stage decimated digital loop filter. The use of parallel sampled multi-stage decimated loop filtering significantly reduces the area and power required by previous analog loop filter based solutions. In addition, the circuit behavior of the digital loop filter can be verified against the architectural level behavior and the digital loop filter parameters are not subject to analog errors and process/voltage/temperature (PVT) variations.
An implementation of the disclosed architecture, however, makes use of an analog phase selection circuit (PSC) that is implemented as a voltage controlled delay line (VCDL). The digital loop filter calculates digital phase adjustments to be made to the various sampling clocks and the VCDL actually changes the phase of the sampling clocks. VCDL errors, however, can degrade the jitter tolerance performance.
In particular, the VCDL introduces static clock timing errors that cause non-uniform spacing of the clock phases. For example, if the desired clock phase resolution is T/32, where T is the baud period, then the 32 phases of the recovered clock are not equally spaced by T/32 for each adjacent phase. In addition, depending on the specifics of the CDR architecture, multiple recovered clocks may be necessary if the architecture uses parallel sampled data or phase detectors requiring oversampling, such as bang-bang phase detectors or their extensions.
A need therefore exists for methods and apparatus for digital compensation of these clock timing errors in the VCDL.